In a semiconductor integrated circuit controlling the internal circuit in synchronism with system clocks, preset circuit operations are executed each clock period to control the internal circuit in its entirety. Recently, the chip size is increased in keeping pace with the tendency towards the increasing degree of integration and towards the higher function of the function of the semiconductor integrated circuit. On the other hand, as the clock period becomes shorter with the increasing operating frequency, the shortening of the delay time difference in the clock path is presenting problems.
In order to cope with this task, there is disclosed in, for example, the JP Patent Kokai JP-A-9-258841 a clock supplying method in which there are provided an oncoming clock line and an outgoing clock line, these clock lines are divided into two lines of forward and return paths, and in which the wiring delay is detected to adjust clocks. There is disclosed a configuration comprising a receiver having first and second input terminals at a first position on the forward path and a second position near the first position on the forward path, respectively. The delay in the forward path and return path is detected from these first and second input terminals to output an average value of the delay caused in the forward and return paths.
That is, in the JP Patent Kokai JP-A-9-258841, a point A of a forward route 111, as an input, is coupled to an end of a phase detection circuit 181 through a variable delay line 171 and a variable delay line 172, a point H of a return route 112, as an input, is coupled to the other end of the phase detection circuit 181, the delay time of the variable delay lines 171, 172 is variably controlled for phase adjustment, and an output of a receiver is derived from a junction point of the variable delay lines 171, 172.
Since the delay time from the point A of the forward route 111 of the clock propagation path up to a turning point 113 is α, the delay time from the point A to the point H is 2a, an average value of the delay time between the points A and H is α, the delay time from the point b of the forward route 111 of the clock transmitting line to the turning point 113 is b and the delay time from the point B to the point G is 2b. So, the sum of the delay time (a−b) from the input end to the point b and the delay time ((a−b)+(a−b)+2b) from the input end to the point G is {(a−b)+((a−b)+(a−b)+2b)} is 2a, with an average value being α. In this manner, clock signals with the corresponding phase can be obtained without dependency on the positions of the clock propagation path.
In this manner, in the conventional method disclosed in the JP Patent Kokai JP-A-9-258841, a clock path is direction-reversed and a delay timing of an intermediate point between the forward and return routes is taken to adjust the delay amount of the variable delay line in the clock path.
For adjusting the delay in this manner, a feedback circuit loop, exemplified by a phase locked loop (PLL) or a delay lock loop (DLL), in which the phase difference is detected by a phase detection circuit and the delay caused in the variable delay line is varied based on the detected phase difference, is routinely used.